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Precision Temperature Monitor for
DDR Memory Modules
2  _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +3.6V, T
A
= -20癈 to +125癈, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25癈.) (Note 1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
All Input and Output Voltages ..................................-0.3V to +6V
Continuous Power Dissipation (T
A
= +70癈)
8-Pin TDFN (derate 16.7mW/癈 above +70癈) ......1333.3mW
8-Pin TSSOP (derate 8.1mW/癈 above +70癈) ........646.7mW
ESD Protection (all pins, Human Body Model) ....................?kV
Junction Temperature......................................................+150癈
Operating Temperature Range .........................-20癈 to +125癈
Storage Temperature Range.............................-65癈 to +150癈
Lead Temperature (soldering, 10s).................................+300癈
Soldering Temperature (reflow).......................................+260癈
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
V
CC
+2.7
+3.6
V
0.125
癈
Temperature Resolution
11
bits
+3V d V
CC
 d +3.6V, +75癈 d T
A
 d +95癈
-1
+1
+3V d V
CC
d +3.6V, +40癈 d T
A
 d +125癈
-2
+2
Temperature Accuracy
+3V d V
CC
d +3.6V, -20癈 d T
A
 d +125癈
-3
+3
癈
Power-On Reset (POR) Threshold
V
CC
 falling edge
2.0
V
POR Threshold Hysteresis
90
mV
Undervoltage-Lockout Threshold
2.4
V
Operating Current
During conversion
0.3
0.5
mA
Standby Current
3
6
礎
Conversion Time
t
CONV
125
ms
Conversion Rate
f
CONV
8
Hz
DIGITAL INTERFACE (Note 2)
Log i
c- Inp
ut H i g h V
ol tag
e ( S C L, S D A)
V
IH
2.1
V
Logic-Input Low Voltage (SCL, SDA)
V
IL
0.8
V
Logic-Input Hysteresis (SCL, SDA)
500
mV
Leakag e C
ur
r ent ( E
V E N
T, S C
L, S D A,
A2, A1, A0)
I
LEAK
V
IN
= V
GND
 or V
CC
-1
+1
礎
Logic-Output Low Voltage
(SDA, EVENT)
V
OL
I
PULL_UP
 = 350礎
50
mV
Logic-Output Low Sink Current
(SDA, EVENT)
I
OL
V
OL
 = 0.6V
6
mA
Input Capacitance (SCL, SDA)
C
IN
5
pF
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